1. Field of the Invention
The invention relates generally to a multiport memory and, more particularly, to an improved cell circuit for data readout for use in a multiport memory.
2. Description of the Related Art
Current microelectronic circuits will achieve complicated systems with a great number of transistors, and the number will keep increasing in the future. Generally, these systems include a plurality of cooperating subsystems for processing data. One apparent problem with realizing these systems is the storage of the data to be processed, as well as their data processing programs. The most powerful systems will surely be realizable if a memory is available to which the subsystems can gain access chronologically parallel and with a high bandwidth. Such memories, which have multiple ports as external terminals, to which the external component units can gain access chronologically parallel, are generally known as multiport memories.
A prior-art multiport memory typically uses a large multiplexer to select one of a plurality of data store cell outputs, resulting in a relatively large space for a readout cell area for multiple read ports as well as a large number of read wordlines. Therefore, a need exists for a multiport memory with new multiple read ports configuration that takes up less space for a readout cell area by reducing both the readout cell area and the number of read wordlines.
The present invention provides a cell circuit for data readout in a multiport memory storing a plurality of write data signals. The cell circuit includes a multiplexer and a discharge device. The multiplexer receives a subset of the write data signals and a plurality of read wordline signals and selects an output enable signal among the subset of the write data signals based on the read wordline signals. The discharge device is coupled to the multiplexer for receiving the output enable signal to generate a drive signal for driving a bitline of the multiport memory.